1. Field of Use
The present invention relates to data processing systems and in particular to systems which include cache memory stores.
2. Prior Art
In some prior art systems, the central processing unit includes a register for controlling the modes of operation. Normally, the register is loaded by a special instruction which is able to turn the cache store on and off which in effect bypasses the store.
In such systems, it therefore becomes necessary to first place the central processing unit in a particular mode which then allows bypassing of the cache memory store. Obvious disadvantages include the additional overhead processing. Moreover, the arrangement is not suitable for systems which can have more than one processing unit access the cache store (e.g. multiprocessing system).
Another prior art system employs a segment memory system which enables, through the use of segment descriptor words, the manner in which segments are to be handled (access attributes). Included in the segment descriptor words are bits which cause the address unit to inhibit the cache from making any successful address comparisons. This enables some segments to have words sorted in the cache store and the cache store to be bypassed by other segments.
In such an arrangement, it is normally required that segments associated with input/output operations are prevented from entering the central processing unit's cache store (operates without cache) in that this could cause the updating of words in main memory which would not be detected.
While this arrangement is more suitable for multiprocessing systems, it still has the disadvantages of overhead expended in establishing which segments are permitting access to the cache store particularly where the segments are to be shared. Also, this places additional restrictions upon main memory addresses and complicates memory management.
Accordingly, it is a primary object of the present invention to provide an improved arrangement for bypassing a cache store.
It is a further object of the present invention to provide a cache store in which any area may be selectively accessed by any one of a number of command modules.